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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad7655 * low cost 4-channel 1 msps 16-bit adc functional block diagram clock and control logic a/ b 16 d[15:0] busy cs ser/ par ognd ovdd dgnd dvdd serial port p arallel interface byteswap rd av d d a gnd refx refgnd pd reset cnvst inan switched cap dac ad7655 ina1 track/hold 2 impulse mux mux eoc mux ina2 a0 inb1 inbn inb2 pulsar selection type/ksps 100?50 500?70 800?000 pseudo ad7651 ad7650/ad7652 ad7653 differential ad7660/ad7661 ad7664/ad7666 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 18-bit ad7678 ad7679 ad7674 multichannel/ ad7654 simultaneous ad7655 product highlights 1. multichannel adc the ad7655 features 4-channel inputs with two sample- and-hold circuits that allow simultaneous sampling. 2. fast throughput the ad7655 is a very high speed (1 msps in normal mode and 888 ksps in impulse mode), charge redistribution, 16-bit sar adc that avoids pipeline delay. 3. single-supply operation the ad7655 operates from a single 5 v supply and dissipates only 120 mw typical, even lower when a reduced throughput is used with the reduced power mode (impulse) and a power- down mode. 4. serial or parallel interface versatile parallel or 2-wire serial interface arrangement compatible with both 3 v or 5 v logic. * patent pending features 4-channel, 16-bit resolution adc 2 track-and-hold amplifiers throughput: 1 msps (normal mode) 888 ksps (impulse mode) analog input voltage range: 0 v to 5 v no pipeline delay parallel and serial 5 v/3 v interface spi /qspi/microwire/dsp compatible single 5 v supply operation power dissipation 120 mw typical, 2.6 mw @ 10 ksps package: 48-lead quad flat pack (lqfp) or 48-lead frame chip scale pack (lfcsp) pin-to-pin compatible with the ad7654 low cost applications 4-channel data acquisition general description the ad7655 is a low cost, 4-channel, 16-bit, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. it contains two low noise, wide bandwidth track-and- hold amplifiers that allow simultaneous sampling, a high speed 1m sps 16-bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. each track-and-hold has a multiplexer in front to provide a 4-channel input adc. the ad7655 features a very high sampling rate mode (normal) and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. it is available in 48-lead lqfp or 48-lead lfcsp packages with operation specified from C 40 c to +85 c.
rev. 0 ? ad7655?pecifications parameter conditions min typ max unit resolution 16 bits analog input voltage range v inx C v inxn 0 2 v ref common-mode input voltage v inxn C 0.1 +0.5 v analog input cmrr f in = 100 khz 55 db input current 1 msps throughput 45 m a input impedance see analog input section throughput speed complete cycle (2 channels) in normal mode 2 m s throughput rate in normal mode 0 1 msps complete cycle (2 channels) in impulse mode 2.25 m s throughput rate in impulse mode 0 888 ksps dc accuracy integral linearity error C 6+6 lsb 1 no missing codes 15 bits transition noise 0.8 lsb full-scale error 2 t min to t max 0.25 0.5 % of fsr full-scale error drift 2 2 ppm/ c unipolar zero error 2 t min to t max 0.25 % of fsr unipolar zero error drift 2 0.8 ppm/ c power supply sensitivity avdd = 5 v 5% 0.8 lsb ac accuracy signal-to-noise f in = 100 khz 86 db 3 spurious free dynamic range f in = 100 khz 98 db total harmonic distortion f in = 100 khz C 96 db signal-to-(noise + distortion) f in = 100 khz 86 db f in = 100 khz, C 60 db input 30 db channel-to-channel isolation f in = 100 khz C 92 db C 3 db input bandwidth 10 mhz sampling dynamics aperture delay 4 2ns aperture delay matching 4 30 ps aperture jitter 4 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 avdd/2 v external reference current drain 1 msps throughput 180 m a digital inputs logic levels v il C 0.3 +0.8 v v ih +2.0 ovdd + 0.3 v i il C 1+1 m a i ih C 1+1 m a digital outputs data format parallel or serial 16-bit straight binary coding pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = C 500 m a ovdd C 0.2 v (?0 c to +85 c, v ref = 2.5 v, avdd = avdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. 0 ad7655 ? parameter conditions min typ max unit power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.25 5.25 5 v operating current 6 1 msps throughput avdd 15.5 ma dvdd 8.5 ma ovdd 100 m a power dissipation 1 msps throughput 6 120 135 mw 20 ksps throughput 7 2.6 mw 888 ksps throughput 7 114 125 mw temperature range 8 specified performance t min to t max C 40 +85 c notes 1 lsb means least significant bit. with the 0 v to 5 v input range, one lsb is 76.294 m v. 2 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full scale, unless otherwise specified. 4 sample tested during initial release. 5 the maximum should be the minimum of 5.25 v and dvdd + 0.3 v. 6 in normal mode. 7 in impulse mode. 8 contact factory for extended temperature range. specifications subject to change without notice. timing specifications parameter symbol min typ max unit refer to figures 8 and 9 convert pulsewidth t 1 5ns time between conversions (normal mode/impulse mode) t 2 2/2.25 m s cnvst low to busy high delay t 3 32 ns busy high all modes except in t 4 1.75/2 m s master serial read after convert mode (normal mode/impulse mode) aperture delay t 5 2ns end of conversions to busy low delay t 6 10 ns conversion time (normal mode/impulse mode) t 7 1.75/2 m s acquisition time t 8 250 ns reset pulsewidth t 9 10 ns cnvst low to eoc high delay t 10 30 ns eoc high for channel a conversion t 11 1/1.25 m s (normal mode/impulse mode) eoc low after channel a conversion t 12 45 ns eoc high for channel b conversion t 13 0.75 m s channel selection setup time t 14 250 ns channel selection hold time t 15 30 ns refer to figures 10, 11, 12, 13, and 14 (parallel interface modes) cnvst low to data valid delay t 16 1.75/2 m s data valid to busy low delay t 17 14 ns bus access request to data valid t 18 40 ns bus relinquish time t 19 515ns a/ b low to data valid delay t 20 40 ns (?0 c to +85 c, v ref = 2.5 v, avdd = avdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. 0 ? ad7655 parameter symbol min typ max unit refer to figures 15 and 16 (master serial interface modes) cs low to sync valid delay t 21 10 ns cs low to internal sclk valid delay t 22 10 ns cs low to sdout delay t 23 10 ns cnvst low to sync delay (read during convert) t 24 250/500 ns (normal mode/impulse mode) sync asserted to sclk first edge delay * t 25 3ns internal sclk period * t 26 23 40 ns internal sclk high * t 27 12 ns internal sclk low * t 28 7ns sdout valid setup time * t 29 4ns sdout valid hold time * t 30 2ns sclk last edge to sync delay * t 31 1 cs high to sync hi-z t 32 10 ns cs high to internal sclk hi-z t 33 10 ns cs high to sdout hi-z t 34 10 ns busy high in master serial read after convert t 35 see table i (normal mode/impulse mode) cnvst low to sync asserted delay t 36 0.75/1 m s (normal mode/impulse mode) sync deasserted to busy low delay t 37 25 ns refer to figures 17 and 18 (slave serial interface modes) external sclk setup time t 38 5ns external sclk active edge to sdout delay t 39 318ns sdin setup time t 40 5ns sdin hold time t 41 5ns external sclk period t 42 25 ns external sclk high t 43 10 ns external sclk low t 44 10 ns * in serial master read during convert mode. see table i for serial master read after convert mode. specifications subject to change without notice. table i. serial clock timings in master read after convert divsclk[1] 0 0 1 1 divsclk[0] symbol 0 101unit sync to sclk first edge delay minimum t 25 3171 717ns internal sclk period minimum t 26 25 50 100 200 ns internal sclk period maximum t 26 40 70 140 280 ns internal sclk high minimum t 27 12 22 50 100 ns internal sclk low minimum t 28 7214 999ns sdout valid setup time minimum t 29 4181 818ns sdout valid hold time minimum t 30 24 30 80 ns sclk last edge to sync delay minimum t 31 13 30 80 ns busy high width maximum (normal) t 35 3.25 4.25 6.25 10.75 m s busy high width maximum (impulse) t 35 3.5 4.5 6.5 11 m s timing specifications (continued)
rev. 0 ad7655 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7655 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 analog inputs inax 2 , inbx 2 , refx, inxn, refgnd agnd . . . . . . . . . . . . . . . . . . . . . . C 0.3 v to avdd + 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . . C 0.3 v to +7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v digital inputs . . . . . . . . . . . . . . . . . C 0.3 v to dvdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . . . 700 mw internal power dissipation 4 . . . . . . . . . . . . . . . . . . . . . . . 2.5 w junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . . C 65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w. 4 specification is for device in free air: 48-lead lfcsp: ja = 26 c/w. ordering guide model temperature range package description package option ad7655ast C 40 c to +85 c quad flatpack (lqfp) st-48 AD7655ASTRL C 40 c to +85 c quad flatpack (lqfp) st-48 ad7655acp C 40 c to +85 cc hip scale pack (lfcsp) cp-48 ad7655acprl C 40 c to +85 cc hip scale pack (lfcsp) cp-48 eval-ad7655cb 1 evaluation board eval-control brd2 2 controller board notes 1 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstrati on purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to output pin c l 60pf * 500 a i oh 1.6ma i ol 1.4v * in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v t dela y 2v 0.8v t delay figure 2. voltage reference levels for timing
rev. 0 ? ad7655 pin function descriptions pin number mnemonic type description 1, 47, 48 agnd p analog power ground pin. 2 avdd p input analog power pin. nominally 5 v. 3a 0d im ultiplexer select. when low, the analog inputs ina1 and inb1 are sampled simultaneously, then converted. when high, the analog inputs ina2 and inb2 are sampled simultaneously, then converted. 4 byteswap di parallel mode selection (8-/16-bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. 5a/ b di data channel selection. in parallel mode, when low, the data from channel b is read. when high, the data from channel a is read. in serial mode, when high, channel a is output first followed by channel b. when low, channel b is output first followed by channel a. 6, 20 dgnd digital power ground pin. 7 impulse di mode selection. when high, this input selects a reduced power mode, impulse. in this mode, the power dissipation is approximately proportional to the sampling rate. when low, the mode normal is selected. 8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9, 10 d[0:1] do bit 0 and bit 1 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. 11, 12 d[2:3] or di/o when ser/ par is low, these outputs are used as bit 2 and bit 3 of the parallel port data output bus. divsclk[0:1] when ser/ par is high, ext/ int is low and rdc/sdin is low which is the serial master read after convert mode, these inputs, part of the serial port, are used to slow down if desired the internal serial clock which clocks the data output. in the other serial modes, these inputs are not used. 13 d[4] di/o when ser/ par is low, this output is used as bit 4 of the parallel port data output bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock, called respectively, master and slave mode. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 d[5] di/o when ser/ par is low, this output is used as bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) dvdd cnvst pd reset cs rd eoc a gnd av d d a0 byteswap a/ b dgnd impulse ser/ par d0 d1 d2/divsclk[0] busy d15 d14 d13 ad7655 d3/divsclk[1] d12 a gnd a gnd ina1 inan ina2 refa refb inb2 inbn inb1 refgnd ref d4/ext/ int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror
rev. 0 ad7655 ? pin function descriptions pin number mnemonic type description 15 d[6] di/o when ser/ par is low, this output is used as bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master and slave mode. 16 d[7] di/o when ser/ par is low, this output is used as bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 32 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the previous data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (5 v or 3 v). 19, 36 dvdd p digital power. nominally at 5 v. 21 d[8] do when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in a 32-bit on-chip register. the ad7655 provides the two conversion results, msb first, from its internal shift register. the order of channel outputs is controlled by a/ b . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on sclk falling edge and valid on the next rising edge. 22 d[9] di/o when ser/ par is low, this output is used as bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 d[10] do when ser/ par is low, this output is used as bit 10 of the parallel port data output bus. or sync when ser/ par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and frames sdout. after the first channel is output, sync is pulsed low. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. after the first channel is output, sync is pulsed high. 24 d[11] do when ser/ par is low, this output is used as bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as a incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25 C 28 d[12:15] do bit 12 to bit 15 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. 29 busy do busy output. transitions high when a conversion is started, and remains high until the two conversions are complete and the data are latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 eoc do end of convert output. going low at each channel conversion. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external serial clock. 33 reset di reset input. when set to a logic high, reset the ad7655. current conversion if any is aborted. if not used, this pin could be tied to dgnd.
rev. 0 ? ad7655 pin function descriptions (continued) pin number mnemonic type description 34 pd di power-down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current one is completed. 35 cnvst di start conversion. a falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. in impulse mode (impulse high), if cnvst is held low when the acquisition phase ( t 8 ) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 37 ref ai this input pin is used to provide a reference to the converter. 38 refgnd ai reference input analog ground 39, 41 inb1, inb2 ai analog inputs 42, 43 refb, refa ai these inputs are the references applied to channel a and channel b, respectively. 40, 45 inbn, inan ai analog input ground senses. allow to sense each channel ground independently. 44, 46 ina2, ina1 ai analog inputs notes ai = analog input di = digital input di/o = bidirectional digital do = digital output p = power definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error t he last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 lsb b elow the nominal full scale (4.999886 v for the 0 v to 5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error in unipolar mode, the first transition should occur at a level 1/2 lsb above analog ground. the unipolar zero error is the devia- tion of the actual transition from that point. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s /( n + d ) by the following formula: enob s n d db =+ [] () ) / C ./. 176 602 and is expressed in bits. total harmonic distortion (thd) t hd is the ratio of the rms sum of the first five harmonic com ponents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signals are held for a conversion. transient response the time required for the ad7655 to achieve its rated accuracy after a full-scale step function is applied to its input.
rev. 0 t ypical performance characteristics?d7655 ? 65536 code inl ? lsb 0 ? ? ? ? ? 2 1 4 3 5 16384 0 32768 49152 tpc 1. integral nonlinearity vs. code code in hex counts 4000 3000 2000 1000 0 102 7059 1094 1230 77 29 0 0 0 0 103 104 105 106 107 108 109 10a 8000 7000 6000 5000 101 6894 tpc 2. histogram of 16,384 conversions of a dc input at the code transition frequency ? khz amplitude ? db of full scale ?140 ?160 ?180 0 25 125 150 50 75 100 175 200 225 250 ?80 ?100 ?120 ?20 ?40 ?60 0 8192 point fft f s = 500mhz f in = 100khz, ?0.5db snr = 85.8db thd = ?91.4db sfdr = 93.6db s/[n+d] = 84.5db tpc 3. fft plot 65536 code dnl ? lsb 0 ? ? ? 1 2 3 16384 0 32768 49152 tpc 4. differential nonlinearity vs. code code in hex counts 4000 3000 2000 1000 0 102 8480 3505 3396 220 739 39 0 0 5 103 104 105 106 107 108 109 10a 9000 8000 7000 6000 5000 tpc 5. histogram of 16,384 conversions of a dc input at the code center r temperature ? c snr ? db 90 87 84 ?15 5 25 45 65 85 105 125 96 93 ?35 ?55 ?98 ?102 ?106 ?90 ?94 thd ? db thd snr tpc 6. snr, thd vs. temperature
rev. 0 ?0 ad7655 frequency ? khz snr and s/[n+d] ? db 85 80 75 70 1 10 100 1000 100 95 90 snr sinad enob ? bits 14.5 14.0 13.5 13.0 16.0 15.5 15.0 enob tpc 7. snr, s/(n+d), and enob vs. frequency frequency ? khz thd, harmonics ? db ?90 ?95 ?100 ?105 ?110 1 10 100 1000 ?75 ?80 ?85 sfdr crosstalk b to a crosstalk a to b thd third harmonic second harmonic tpc 8. thd, harmonics, crosstalk and sfdr vs. frequency ?55 565 125 temperature ? c lsb 0 ?4 ?5 ?2 ?3 ?1 2 1 4 3 5 25 ?35 ?15 45 85 105 full scale offset drift tpc 9. full scale and zero error vs. temperature operating currents ? ma 10 1 0.1 100 sampling rate ? ksps 10 100 1000 1 normal avdd normal dvdd impulse avdd ovdd 2.7v 0.01 0.001 0.0001 impulse dvdd tpc 10. operating currents vs. sample rate c l ? pf t 12 delay ? ns 20 10 0 05 0 100 1000 50 40 30 ovdd = 2.7v @ 85 c ovdd = 2.7v @ 25 c ovdd = 5v @ 85 c ovdd = 5v @ 25 c 150 tpc 11. typical delay vs. load capacitance c l
rev. 0 ad7655 ?1 circuit information the ad7655 is a very fast, low power, single-supply, precise 4-channel 16-bit analog-to-digital converter (adc). the ad7655 provides the user with two on-chip track-and-hold, successive approximation adcs that do not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. the ad7655 can be operated from a single 5 v supply and can be interfaced to either 5 v or 3 v digital logic. it is housed in a 48-lead lqfp or in a tiny 48-lead lfcsp package that combines space savings and allows flexible configurations as either serial or parallel interface. the ad7655 is pin-to-pin compatible with pulsar adcs. modes of operation the ad7655 features two modes of operation, normal and impulse. each of these modes is more suitable for specific applications. the normal mode is the fastest mode (1 msps). except when it is powered down (pd high), the power dissipation is almost independent of the sampling rate. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maximum throughput in this mode is 888 ksps. when operating at 20 ksps, for example, it typically consumes only 2.6 mw. this feature makes the ad7655 ideal for battery-powered applications. transfer functions the ad7655 data format is straight binary. the ideal transfer characteristic for the ad7655 is shown in figure 3 and table ii. 000...000 000...001 000...010 111...101 111...110 111...111 analog input +f s ? 1.5 lsb +fs ? 1 lsb ?fs + 1 lsb ?fs ?fs + 0.5 lsb adc code ? straight binary figure 3. adc ideal transfer function table ii. output codes and ideal input voltages analog digital output d escription input v ref = 2.5 v code (hex) fsr C 1 lsb 4.999924 v ffff 1 fsr C 2 lsb 4.999847 v fffe midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale C 1 lsb 2.499924 v 7fff C fsr + 1 lsb C 76.29 m v0 001 C fsr 0 v 0000 2 notes 1 this is also the code for overrange analog input (v inx C v inxn above 2 (v ref C v refgnd )). 2 this is also the code for underrange analog input (v inx below v inxn ).
rev. 0 ?2 ad7655 av d d a gnd dgnd dvdd ovdd ognd ser/ par cnvst busy sdout sclk rd cs reset pd refgnd c ref 2.5v ref note 1 ref a/ ref b/ ref 30 d clock ad7655 c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd a/ b note 7 byteswap dvdd 50k 100nf 1m ina1 c c 2.7nf u1 note 4 note 5 50 ad8021 ? + 15 2.7nf u2 note 4 note 5 50 ad8021 ? + 15 inan ina2 note 2 note 3 note 6 ad780 10 f 100nf + 10 f 100nf + 100nf + 10 f 50 + 1 f notes 1. see voltage reference input section. 2. with the recommended voltage references, c ref is 47 f. see voltage reference input section. 3. optional circuitry for hardware gain calibration. 4. the ad8021 is recommended. see driver amplifier choice section. 5. see analog inputs section. 6. option, see power supply section. 7. optional low jitter cnvst . see conversion control section. a0 inb1 2.7nf u1 note 4 note 5 50 ad8021 ? + 15 inbn 2.7nf u2 note 4 note 5 50 ad8021 ? + 15 inb2 analog input a1 analog input a2 analog input b1 analog input b2 c c c c c c figure 4. typical connection diagram (serial interface)
rev. 0 ad7655 ?3 typical connection diagram figure 4 shows a typical connection diagram for the ad7655. different circuitry shown on this diagram is optional and is discussed below. analog inputs figure 5 shows a simplified analog input section of the ad7655. ina1 r a = 500 inb2 r b = 500 c s c s a gnd av d d ina2 inan inbn inb1 figure 5. simplified analog input the diodes shown in figure 5 provide esd protection for the inputs. care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. this will cause these diodes to become forward-biased and start conducting current. these diodes can handle a forward-biased current of 120 ma maximum. this condition could eventually occur when the input buffer s (u1) or (u2) supplies are different from avdd. in such a case, an input buffer with a short-circuit current lim ita tion can be used to protect the part. this analog input structure allows the sampling of the differential signal between inx and inxn. unlike other converters, the inxn is sampled at the same time as the inx input. by using these differ- ential inputs, small signals common to both inputs are rejected. during the acquisition phase, for ac signals, the ad7655 behaves like a one-pole rc filter consisting of the equivalent resistance r a , r b , and c s . the resistors r a and r b are typically 500 w and are a lumped component made up of some serial resistance and the on resistance of the switches. the capacitor c s is typically 32 pf and is mainly the adc sampling capacitor. this one-pole filter with a typical C 3 db cutoff frequency of 10 mhz reduces unde- sirable aliasing effects and limits the noise coming from the inputs. because the input impedance of the ad7655 is very high, the ad7655 can be driven directly by a low impedance source without gain error. as shown in figure 4, that allows an external one-pole rc filter between the output of the amplifier output and the adc analog inputs to even further improve the noise filtering done by the ad7655 analog input circuit. however, the source impedance has to be kept low because it affects the ac perfor- mances, especially the total harmonic distortion. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd degrades with the increase of the source impedance. driver amplifier choice although the ad7655 is easy to drive, the driver amplifier needs to meet at least the following requirements: the driver amplifier and the ad7655 analog input circuit have to be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). in the amplifier s data sheet, the settling at 0.1% or 0.01% is more commonly specified. it could significantly differ from the settling time at a 16-bit level and, therefore, it should be verified prior to the driver selection. the tiny op amp ad8021, which combines ultra- low noise and a high gain bandwidth, meets this settling time requirement even when used with a high gain of up to 13. the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transition noise performance of the ad7655. the noise coming from the driver is filtered by the ad7655 analog input circuit one-pole low-pass filter made by r a , r b , and c s . the driver needs to have a thd performance suitable to that of the ad7655. the ad8021 meets these requirements and is usually appropriate for almost all applications. the ad8021 needs an external compensation capacitor of 10 pf. this capacitor should have good linearity as an npo ceramic or mica type. the ad8022 could also be used where a dual version is needed and a gain of 1 is used. the ad829 is another alternative where high frequency (above 100 khz) performance is not required. in a gain of 1, it requires an 82 pf compensation capacitor. the ad8610 is also an option where low bias current is needed in low frequency applications. voltage reference input the ad7655 requires an external 2.5 v reference. the reference input should be applied to ref, refa for channel a, and to refb for channel b. the voltage reference input ref of the ad7655 has a dynamic input impedance; it should therefore be driven by a low impedance source with an efficient decoupling. this decoupling depends on the choice of the voltage reference but usually consists of a 1 m f ceramic capacitor and a low esr tantalum capacitor connected to the refa, refb, and refgnd inputs with minimum parasitic inductance. 47 m f is an appro- priate value for the tantalum capacitor when using one of the recommended reference voltages: the low noise, low temperature drift ad780 voltage reference the low cost ad1582 voltage reference for applications using multiple ad7655s, it is more effective to buffer the reference voltage using the internal buffer. each adc should be decoupled individually. care should also be taken with the reference temperature coeffi- cient of the voltage reference, which directly affects the full-scale accuracy if this parameter is applicable. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. power supply the ad7655 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and dvdd + 0.3 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply, as shown in figure 5. the ad7655 is independent of power supply sequencing, once ovdd does not exceed dvdd by more than 0.3 v, and thus is free from supply voltage induced latchup. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 6.
rev. 0 ?4 ad7655 frequency ? khz 40 110 psrr ? db 100 1000 10000 45 50 55 60 65 70 figure 6. psrr vs. frequency power dissipation in impulse mode, the ad7655 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows significant power savings when the conversion rate is reduced, as shown in figure 7. this feature makes the ad7655 ideal for very low power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., dvdd and dgnd) and ovdd should not exceed dvdd by more than 0.3 v. sampling rate ? ksps 0.1 110 power dissipation ? mw 100 1000 1 10 100 1000 normal impulse figure 7. power dissipation vs. sample rate conversion control figure 8 shows the detailed timing diagrams of the conversion process. the ad7655 is controlled by the signal cnvst , which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conversion is complete. the cnvst signal operates independently of the cs and rd signals. the a0 signal is the mux select signal that chooses which input signal is to be sampled. when high, inx1 is chosen and when low, inx2 is chosen, where x is either a or b. it should be noted that this signal should not be changed during the acquisition phase of the converter. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert a acquire convert convert b eoc t 12 a0 t 14 t 15 t 13 t 11 t 10 figure 8. conversion control in impulse mode, conversions can be automatically initiated. if cnvst is held low when busy is low, the ad7655 controls the acquisition phase and then automatically initiates a new conversion. by keeping cnvst low, the ad7655 keeps the conversion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7655 could sometimes run slightly faster than the guaranteed limits in the impulse mode of 888 ksps. this feature does not exist in normal mode. although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels, and with minimum overshoot and undershoot or ringing. for applications where the snr is critical, the cnvst signal should have a very low jitter. some solutions to achieve this are to u se a dedicated oscillator for cnvst generation or, at least, to clock it with a high frequency low jitter clock, as shown in figure 4. t 9 reset data bus busy cnvst t 8 figure 9. reset timing digital interface the ad7655 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7655 digital interface also accommodates either 3 v or 5 v logic by simply connecting the ovdd supply pin of the ad7655 to the host system interface digital supply.
rev. 0 ad7655 ?5 signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7655 in multicircuit applications and is held low in a single ad7655 design. rd is generally used to enable the conversion result on the data bus. in parallel mode, signal a/ b allows the choice of reading either the output of channel a or channel b, whereas in serial mode, signal a/ b controls which channel is output first. t 1 t 3 t 4 t 17 cnvst busy data bus cs = rd = 0 t 16 new a or b eoc previous channel a or b previous channel b or new a t 10 figure 10. master parallel data timing for reading (continuous read) data bus t 18 t 19 busy cs rd current conversion figure 11. slave parallel data timing for reading (read after convert) previous conversion t 1 t 3 t 18 t 19 t 4 cs = 0 cnvst , rd busy data bus eoc t 13 t 11 t 12 t 10 figure 12. slave parallel data timing for reading (read during convert) parallel interface the ad7655 is configured to use the parallel interface (figure 10) when ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase or during the other channel s conversion, or during the following conversion as shown, respectively, in figures 11 and 12. when the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. that avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. the byteswap pin allows a glueless interface to an 8-bit bus. as shown in figure 13, the lsb byte is output on d[7:0] and the msb is output on d[15:8] when byteswap is low. when byteswap is high, the lsb and msb bytes are swapped, the lsb is output on d[15:8], and the msb is output on d[7:0]. by connecting byteswap to an address line, the 16-bit data can be read in two bytes on either d[15:8] or d[7:0]. cs rd byte pins d[15:8] pins d[7:0] hi-z hi-z high byte low byte low byte high byte hi-z hi-z t 18 t 18 t 19 figure 13. 8-bit parallel interface cs a/ b rd hi-z channel a t 18 data bus t 20 channel b hi-z figure 14. a/ b channel reading the detailed functionality of a/ b is explained in figure 14. when high, the data from channel a is available on the data bus. when low, the data bus now carries output from channel b. note that channel a can be read immediately after conversion is done ( eoc ), while channel b is still in its converting phase. serial interface the ad7655 is configured to use the serial interface when ser/ par is held high. the ad7655 outputs 32 bits of data, msb first, on the sdout pin. the order of the channels being output is controlled by a/ b . when high, channel a is output first; when low, channel b is output first. unlike in parallel mode, channel a data is updated only after channel b conversion. this data is synchronized with the 32 clock pulses provided on the sclk pin.
rev. 0 ?6 ad7655 master serial interface internal clock the ad7655 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7655 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. the output data is valid on both the rising and falling edge of the data clock. depending on rdc/sdin input, the data can be read after each conversion or during the following conversion. figures 15 and 16 show the detailed timing diagrams of these two modes. usually, because the ad7655 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used. in read after conversion mode, it should be noted that unlike in other modes, the signal busy returns low after the 32 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. one advantage of this mode is t 3 busy cs , rd cnvst sync sclk sdout 1216 30 31 32 ch a d15 ch a d14 ch b d2 ch b d1 ch b d0 x ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 21 t 27 t 22 t 23 t 29 t 30 t 36 t 25 t 28 t 37 t 32 t 31 t 33 t 34 a/ b = 1 eoc t 12 t 13 17 t 35 t 26 figure 15. master serial data timing for reading (read after convert) ext/ int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 24 t 21 t 26 t 27 t 28 t 31 t 33 t 32 t 34 t 30 t 29 t 23 t 22 ch a d15 x 12 16 1 2 t 25 busy sync sclk sdout cs , rd cnvst 16 ch b d15 ch a d0 ch a d14 ch b d14 ch b d0 a/ b = 1 eoc t 10 t 11 t 13 t 12 figure 16. master serial data timing for reading (read previous conversion during convert)
rev. 0 ad7655 ?7 that it can accommodate slow digital hosts because the serial clock can be slowed down by using divsclk. in read during conversion mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. the sync signal goes low after the lsb of each channel has been output. slave serial interface external clock the ad7655 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs and the data are output when both cs and rd are low. thus, depending on cs , the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figures 17 and 18 show the detailed timing diagrams of these methods. while the ad7655 is performing a bit decision, it is important that voltage transients do not occur on digital input/output pins or degradation of the conversion result could occur. this is particu- larly im portant during the second half of the conversion phase of each channel because the ad7655 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recom- mended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low or, more importantly, that it does not transition during the latter half of eoc high. cs sclk sdout ch a d15 busy sdin invsclk = 0 t 42 t 43 t 44 t 38 t 39 t 23 t 40 t 41 x 123 30313 233 34 ext/ int = 1 ch b d0 ch b d1 ch a d13 ch a d14 x ch a d14 x ch a d15 x ch a d13 x ch a d14 x ch a d15 x ch b d0 x ch b d1 y ch a d14 y ch a d15 rd = 0 a/ b = 1 eoc figure 17. slave serial data timing for reading (read after convert) cnvst sdout sclk x ch a d15 123 3132 t 3 t 42 t 43 t 44 t 38 t 39 t 23 busy invsclk = 0 cs ext/ int = 1 ch b d0 ch b d1 ch a d13 ch a d14 rd = 0 eoc t 10 t 11 t 13 t 12 a/ b = 1 figure 18. slave serial data timing for reading (read previous conversion during convert)
rev. 0 ?8 ad7655 external discontinuous clock data read after conversion this mode is the most recommended of the serial slave modes. figure 18 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the results of this conversion can be read while both cs and rd are low. the data from both channels are shifted out, msb first, with 32 clock pulses and are valid on both the rising and falling edge of the clock. among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is to be able to read the data at any speed up to 40 mhz, which accommodates both slow digital host interface and the fastest serial reading. finally, in this mode only, the ad7655 provides a daisy-chain feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing component count and wiring connections when it is desired, as it is for instance in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 19. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the opposite edge of sclk of the one used to shift out the data on sdout. therefore, the msb of the upstream converter follows the lsb of the downstream converter on the next sclk cycle. external clock data read during conversion figure 18 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out, msb first, with 32 clock pulses, and is valid on both rising and falling edges of the clock. the 32 bits have to be read before the current conversion is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy-chain feature in this mode, and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock is recommended to ensure that all the bits are read during the first half of the conversion phase. it is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. busy busy ad7655 #2 (upstream) ad7655 #1 (downstream) rdc/sdin sdout cnvst cs sclk rdc/sdin sdout cnvst cs sclk data out sclk in cs in cnvst in busy out figure 19. two ad7655s in a daisy-chain configuration microprocessor interfacing the ad7655 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the ad7655 is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7655 to prevent digital noise from coupling into the adc. the following section illustrates the use of the ad7655 with an spi equipped dsp, the adsp-219x.
rev. 0 ad7655 ?9 spi interface (adsp-219x) figure 20 shows an interface diagram between the ad7655 and an spi equipped dsp, adsp-219x. to accommodate the slower speed of the dsp, the ad7655 acts as a slave device and data must be read after conversion. this mode also allows the daisy chain feature. the convert command could be initiated in response to an internal timer interrupt. the 32-bit output data are read with two spi 16-bit wide access. the reading process could be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the dsp. the serial peripheral interface (spi) on the adsp-219x is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1 by writing to the spi control register (spicltx). ad7655 * adsp-219x * ser/ par pfx misox sckx pfx or tfsx busy sdout sclk cnvst ext/ int cs rd invsclk dvdd * additional pins omitted for clarity spixsel (pfx) figure 20. interfacing the ad7655 to spi interface application hints layout the ad7655 has very good immunity to noise on the power supplies, as seen in figure 5. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7655 should be designed so the analog and digital sections are separated and con- fined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7655, or at least as close as possible to the ad7655. if the ad7655 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point, which should be estab- lished as close as possible to the ad7655. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7655 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sec- tions of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad7655 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supply s impedance presented to the ad7655 and reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supply s pins, avdd, dvdd, and ovdd close to and ideally right up against these pins and their corre- sponding ground pins. additionally, low esr 10 m f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the ad7655 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recom- mended if there is no separate supply available to connect the dvdd digital supply to the analog supply avdd through an rc filter, as shown in figure 5, and connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7655 has four different ground pins: refgnd, agnd, dgnd, and ognd. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. t his ground m ust be con- nected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is impor- tant. the decoupling capacitor should be close to the adc and connected with short and large traces to minimize parasitic inductances. evaluating the ad7655 performance a recommended layout for the ad7655 is outlined in the documen- tation of the evaluation board for the ad7655. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control brd2.
rev. 0 c03536??/03(0) printed in u.s.a. ?0 ad7655 outline dimensions 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane 48-lead lead frame chip scale package [lfcsp] (cp-48) dimensions shown in millimeters pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 bottom view 5.25 5.10 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 1.00 max 0.65 nom 1.00 0.90 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 sq seating plane compliant to jedec standards mo-220-vkkd-2

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